View AD10200_224946.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

a
Dual Channel, 12-Bit 105 MSPS IF Sampling A/D Converter with Analog Input Signal Conditioning AD10200
includes two wide-dynamic range ADCs. Each ADC has a transformer coupled front-end optimized for Direct-IF sampling. The AD10200 has on-chip track-and-hold circuitry, and utilizes an innovative architecture to achieve 12-bit, 105 MSPS performance. The AD10200 uses innovative high-density circuit design to achieve exceptional matching and performance while still maintaining excellent isolation, and providing for significant board area savings. The AD10200 operates with 5.0 V supply for the analog-todigital conversion. Each channel is completely independent allowing operation with independent encode and analog inputs. The AD10200 is packaged in a 68-lead ceramic chip carrier package. Manufacturing is done on Analog Devices, Inc. MIL38534 Qualified Manufacturers Line (QML) and components are available up to Class-H (-55C to +125C).
PRODUCT HIGHLIGHTS
FEATURES Dual, 105 MSPS Minimum Sample Rate Channel-Channel Isolation, >80 dB AC-Coupled Signal Conditioning Included Gain Flatness up to Nyquist: < 0.2 dB Input VSWR 1.1:1 to Nyquist 80 dB Spurious-Free Dynamic Range Two's Complement Output Format 3.3 V or 5 V CMOS-Compatible Output Levels 0.850 W per Channel Industrial and Military Grade APPLICATIONS Radar IF Receivers Phased Array Receivers Communications Receivers Secure Communications GPS Antijamming Receivers Multichannel, Multimode Receivers PRODUCT DESCRIPTION
1. Guaranteed sample rate of 105 MSPS. 2. Input signal conditioning with full power bandwidth to 250 MHz. 3. Fully tested/characterized performance at 121 MHz AIN. 4. Optimized for IF sampling.
The AD10200 is a full channel ADC solution with on-module signal conditioning for improved dynamic performance and fully matched channel-to-channel performance. The module
FUNCTIONAL BLOCK DIAGRAM
AINA2
7
AINB2
63
D00A 34 (LSB) D01A 33 T1A D02A 32 D03A 31 D04A 30 D05A 29 D06A 28 D07A 25 D08A 24 D09A 23 D10A 22 D11A 21 (MSB) TIMING REF REF TIMING OUTPUT RESISTORS OUTPUT RESISTORS 12 ADC 12 ADC 12 12 T/H 50 50 T1B
50 D00B
(LSB)
49 D01B 48 D02B 47 D03B 46 D04B
AD10200
T/H
45 D05B 42 D06B 41 D07B 40 D08B 39 D09B 38 D10B 37 D11B
(MSB)
18
17
3
56
53
54
ENCODEA ENCODEA
REF_A_OUT
REF_B_OUT
ENCODEB
ENCODEB
REV. A
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 www.analog.com Fax: 781/326-8703 (c) Analog Devices, Inc., 2001
AD10200-SPECIFICATIONS1 (V
Parameter RESOLUTION DC ACCURACY Differential Nonlinearity Integral Nonlinearity No Missing Codes Gain Error2 Output Offset ANALOG INPUT Input Voltage Range Input Impedance Input VSWR3 Analog Input Bandwidth, High Analog Input Bandwidth, Low ANALOG REFERENCE Output Voltage Load Current Tempco SWITCHING PERFORMANCE Maximum Conversion Rate Minimum Conversion Rate Duty Cycle Aperture Delay (tA) Aperture Uncertainty (Jitter) Output Valid Time (tV)4 Output Propagation Delay (PD)4 Output Rise Time (tR) Output Fall Time (tF) DIGITAL INPUTS Encode Input Common Mode Differential Input (Enc, Enc) Logic "1" Voltage Logic "0" Voltage Input Resistance Input Capacitance DIGITAL OUTPUTS Logic "1" Voltage4 Logic "0" Voltage4 Output Coding POWER SUPPLY5 Power Dissipation6 Power Supply Rejection Ratio I (DVDD) Current I (AVCC) Current DYNAMIC PERFORMANCE Signal-to-Noise Ratio (SNR)7 (Without Harmonics) fIN = 10 MHz fIN = 41 MHz fIN = 71 MHz fIN = 121 MHz Full Full Full Full Full 25C 25C Full Full Full Full 25C Full Full Full Full 25C 25C Full Full 25C 25C Full Full Full Full Full 25C Full Full Temp
DD =
3.3 V, VCC = 5.0 V; ENCODE = 105 MSPS, unless otherwise noted)
MIL Subgroup Min Typ 12 Max Unit Bits +0.99 +3 +9 +12 LSB LSB % FS LSB V p-p Ratio MHz MHz V mA ppm/C MSPS MSPS % ns ps rms ns ns ns ns V V V V k pF V V
Test Level
IV IV I I I V V IV IV IV I V V I IV IV V V IV IV V V IV IV IV IV IV V VI VI
12 12 1, 2, 3 1, 2, 3 1, 2, 3
-0.99 -3 -9 -12
0.5 0.75 Guaranteed 1
12 12 12 1, 2, 3
200 1 2.4
2.048 50 1.1:1 250
1.25:1
2.5 5 50
2.6
4, 5, 6 12 12
105 45 50 1.0 0.25 5.3 5.5 3.5 3.3 1.6 10 55
12 12 12 12 12 12 12 12 12
3.0 4.5
8.0
1.2 0.4 2.0 3
2.0 5.0 0.8 8
5 4.5
1, 2, 3 1, 2, 3
3.1
3.3 0 0.2 Two's Complement 1800 0.5 25 340 2200 5 40 410
Full Full Full Full
I IV I I
1, 2, 3 12 1, 2, 3 1, 2, 3
mW mV/V mA mA
25C Full 25C Full 25C Full 25C Full
V V I II I II I II
4 5, 6 4 5, 6 4 5, 6
64 62 62.5 61.5 61 61
67 66 66.5 65 66.4 64 65 64
dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS
-2-
REV. A
AD10200
Parameter DYNAMIC PERFORMANCE (Continued) Signal-to-Noise Ratio (SINAD)8 (With Harmonics) fIN = 10 MHz fIN = 41 MHz fIN = 71 MHz fIN = 121 MHz Spurious Free Dynamic Range9 fIN = 10 MHz fIN = 41 MHz fIN = 71 MHz fIN = 121 MHz Two-Tone Intermodulation Distortion10 (IMD) fIN = 10 MHz; fIN = 12 MHz fIN = 71 MHz; fIN = 72 MHz fIN = 121 MHz; fIN = 122 MHz Channel-to-Channel Isolation11 fIN = 121 MHz Temp Test Level MIL Subgroup Min Typ Max Unit
25C Full 25C Full 25C Full 25C Full 25C Full 25C Full 25C Full 25C Full
V V I II I II I II V V I II I II I II
4 5, 6 4 5, 6 4 5, 6
63 60.5 61 57 56 53
66 63 65.5 63 63.5 60 58.5 55 81 70 81 74 65 58
dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS
4 5, 6 4 5, 6 4 5, 6
73 67.5 67 60 61 55.5
25C Full 25C Full 25C Full Full
V V V V I II IV
4 5, 6 12
55.5 53 80
86 81 70 65 62 57 85
dBc dBc dBc dBc dBc dBc dB
NOTES 1 All ac specifications tested by driving ENCODE and ENCODE differentially. 2 Gain Error measured at 2.5 MHz. 3 Input VSWR guaranteed 10 MHz to 200 MHz. 4 tV and tPD are measured from the transition points of the ENCODE input to the 50%/50% levels of the digital outputs swing. The digital output load during test is not to exceed an ac load of 10 pF or a dc current of 40 mA. 5 Supply voltages should remain stable within 5% for normal operation. 6 Power dissipation measured with encode at rated speed and 0 dBm analog input. 7 Analog Input signal power at -1 dBFS; signal-to-noise ratio (SNR) is the ratio of signal level to total noise (first 5 harmonic removed). Encode = 105 MSPS. SNR is reported in dBFS, related back to converter full scale. 8 Analog Input signal power at -1 dBFS; signal-to-noise and distortion (SINAD) is the ratio of signal level to total noise + harmonics. Encode = 105 MSPS. SINAD is reported in dBFS, related back to converter full scale. 9 Analog Input signal equal -1 dBFS; SFDR is ratio of converter full scale to worst spur. 10 Both input tones at -7 dBFS; two tone intermodulation distortion (IMD) rejection is the ratio of either tone to the worst third order intermod product. f1 = x MHz 100 kHz, f2 = x MHz 100 kHz. 11 Channel-to-Channel isolation tested with A Channel/50 terminated (AINA2) grounded and a full-scale signal applied to B Channel (A INB2). Specifications subject to change without notice.
REV. A
-3-
AD10200
ABSOLUTE MAXIMUM RATINGS 1, 2 Table I. Output Coding (VREF = 2.5 V) (Two's Complement)
VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 V VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 V Analog Inputs . . . . . . . . . . . . . . . . . . . . . . . . 5 V p-p(18 dBm) Digital Inputs . . . . . . . . . . . . . . . . . . . -0.5 V to VDD + 0.5 V Digital Output Current . . . . . . . . . . . . . . . . . . . . . . . . 20 mA Operating Temperature . . . . . . . . . . . . . . . . -55C to +125C Storage Temperature . . . . . . . . . . . . . . . . . . -65C to +150C Maximum Junction Temperature . . . . . . . . . . . . . . . . . 175C Maximum Case Temperature . . . . . . . . . . . . . . . . . . . . 150C
NOTES 1 Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions outside of those indicated in the operation sections of this specification is not implied. Exposure to absolute maximum ratings for extended periods may affect device reliability. 2 Typical thermal impedances for "Z" package: JC = 2.22C/W; JA = 24.3C/W.
Code +2047 * * 0 -1 * * -2048
AIN (V) +1.024 * * 0 -0.00049 * * -1.024
Digital Output 0111 1111 1111 * * 0000 0000 0000 1111 1111 1111 * * 1000 0000 0000
EXPLANATION OF TEST LEVELS Test Level
I. II.
100% production tested. 100% production tested at 25C and sample tested at specific temperatures. III. Sample tested only. IV. Parameter is guaranteed by design and characterization testing. V. Parameter is a typical value only. VI. 100% production tested at 25C; guaranteed by design and characterization testing for industrial temperature range.
ORDERING GUIDE
Model AD10200BZ 5962-9961002HXA 5962-9961001HXA AD10200/PCB
Temperature Range -40C to +85C (Case) -40C to +85C (Case) -55C to +125C (Case)
Package Description 68-Lead Ceramic Leaded Chip Carrier 68-Lead Ceramic Leaded Chip Carrier 68-Lead Ceramic Leaded Chip Carrier Evaluation Board with AD10200BZ
Package Option Z-68B Z-68B Z-68B
CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD10200 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
-4-
REV. A
AD10200
PIN CONFIGURATION
DNC VREF_A_OUT
SHIELD
AGNDA
AGNDB
AGNDA
AGNDA
AVCC AGNDB
DNC AINA2 NC
AINB2
9
8
7
6
5
4
3
2
1 68 67 66 65 64 63 62 61 PIN 1 IDENTIFIER 60 59
AGNDA 10 AGNDA 11 DNC 12 AGNDA 13 AVCC 14 DNC 15 AGNDA 16 ENCODEA 17 ENCODEA 18 AGNDA 19 DVCC 20 (MSB) D11A 21 D10A 22 D9A 23 D8A 24 D7A 25 DGNDA 26
NC
AGNDB
DNC
DNC
AGNDB AGNDB 58 DNC
57 56
DNC REF_B_OUT 55 AGNDB
54
AD10200
TOP VIEW (Not to Scale)
ENCODEB ENCODEB 52 AGNDB 51 DV CC
53 50 49
D0B (LSB)
D1B 48 D2B 47 D3B
46 45
D4B D5B 44 DGNDB
27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43
DGNDA D6A D5A D4A D3A
D2A
D1A
AGNDA AGNDB (MSB) D11B D10B
D9B
D8B
D7B D6B
NC = NO CONNECT
PIN FUNCTION DESCRIPTIONS
Pin No. 1 2, 5, 9-11, 13, 16, 19, 35 3 6, 62 7 4, 8, 12, 15, 57, 58, 64, 67 14, 66 17 18 20 21-25, 28-34 26, 27 36, 52, 55, 59-61, 65, 68 37-42, 45-50 43, 44 51 53 54 56 63
Mnemonic SHIELD AGNDA VREF_A_OUT NC AINA2 DNC AVCC ENCODEA ENCODEA DVCC D11A-D7A, D6A-D0A DGNDA AGNDB D11B-D6B, D5B-D0B DGNDB DVCC ENCODEB ENCODEB VREF_B_OUT AINB2
Function Internal Ground Shield between Channels A Channel Analog Ground. A and B grounds should be connected as close to the device as possible. A Channel Internal Voltage Reference No Connection Analog Input for A Side ADC Do Not Connect Analog Positive Supply Voltage (Nominally 5.0 V) Complement of Encode Data conversion initiated on the rising edge of ENCODE input. Digital Positive Supply Voltage (Nominally 3.3 V) Digital Outputs for ADC A. D0 (LSB) A Channel Digital Ground B Channel Analog Ground. A and B grounds should be connected as close to the device as possible. Digital Outputs for ADC B. D0 (LSB) B Channel Digital Ground Digital Positive Supply Voltage (Nominally 3.3 V) Data conversion initiated on rising edge of ENCODE input. Complement of Encode B Channel Internal Voltage Reference Analog Input for B Side ADC
REV. A
(LSB) D0A
-5-
DGNDB
AD10200
DEFINITION OF SPECIFICATIONS Analog Bandwidth Overvoltage Recovery Time
The analog input frequency at which the spectral power of the fundamental frequency (as determined by the FFT analysis) is reduced by 3 dB.
Aperture Delay
The amount of time required for the converter to recover to 0.02% accuracy after an analog input signal of the specified percentage of full scale is reduced to midscale.
Power Supply Rejection Ratio
The delay between the 50% point on the rising edge of the ENCODE command and the instant at which the analog input is sampled.
Aperture Uncertainty (Jitter)
The ratio of a change in output offset voltage to a change in power supply voltage.
Signal-to-Noise-and-Distortion (SINAD)
The sample-to-sample variation in aperture delay.
Differential Nonlinearity
The deviation of any code from an ideal 1 LSB step.
Encode Pulsewidth/Duty Cycle
The ratio of the rms signal amplitude (set a 1 dB below full scale) to the rms value of the sum of all other spectral components, excluding the first five harmonics and dc. [May be reported in dBc (i.e., degrades as signal levels is lowered) or in dBFS (always related back to converter full scale)].
Signal-to-Noise Ratio (without Harmonics)
Pulsewidth high is the minimum amount of time that the ENCODE pulse should be left in Logic "1" state to achieve rated performance; pulsewidth low is the minimum time ENCODE pulse should be left in low state. At a given clock rate, these specs define an acceptable Encode duty cycle.
Harmonic Distortion
The ratio of the rms signal amplitude (set a I dB below full scale) to the rms value of the sum of all other spectral components, excluding the first five harmonics and dc. [May be reported in dBc (i.e., degrades as signal levels is lowered) or in dBFS (always related back to converter full scale).]
Spurious-Free Dynamic Range
The ratio of the rms signal amplitude to the rms value of the worst harmonic component.
Integral Nonlinearity
The deviation of the transfer function from a reference line measured in fractions of 1 LSB using a "best straight line" determined by a least square curve fit.
Minimum Conversion Rate
The ratio of the rms signal amplitude to the rms value of the peak spurious spectral component. The peak spurious component may or may not be a harmonic. [May be reported in dBc (i.e., degrades as signal levels is lowered) or in dBFS (always related back to converter full scale).]
Transient Response
The encode rate at which the SNR of the lowest analog signal frequency drops by no more that 3 dB below the guaranteed limit.
Maximum Conversion Rate
The time required for the converter to achieve 0.02% accuracy when a one-half full-scale step function is applied to the analog input.
Two-Tone Intermodulation Distortion Rejection
The encode rate at which parametric testing is performed.
Output Propagation Delay
The ratio of the rms value of either input tone to the rms value of the worst third order intermodulation product; reported in dBc.
Voltage Standing-Wave Ratio (VSWR)
The delay between the 50% point of the rising edge of ENCODE command and the time when all output data bits are within valid logic levels.
The ratio of the amplitude of the elective field at a voltage maximum to that at an adjacent voltage minimum.
-6-
REV. A
Typical Performance Characteristics-AD10200
0 10 20 30 40 50
0
ENCODE = 105 MSPS AIN = 10MHz (-1dBFS) SNR = 66.84dBFS SFDR = 82.28dBc
10 20 30 40 50
ENCODE = 105 MSPS AIN = 41MHz (-1dBFS) SNR = 66.06dBFS SFDR = 80.59dBc
dB
70
80 90 100 110 120 130
dB
0 5 10 15 20 25 30 35 FREQUENCY - MHz 40 45 50
60
60 70
80 90 100 110 120 130
0
5
10
15
20 25 30 35 FREQUENCY - MHz
40
45
50
TPC 1. Single Tone @ 10 MHz
TPC 4. Single Tone @ 41 MHz
0 10 20 30 40 50
0
ENCODE = 105 MSPS AIN = 71MHz (-1dBFS) SNR = 66.04dBFS SFDR = 79.71dBc
10 20 30 40 50
ENCODE = 105 MSPS AIN = 121MHz (-1dBFS) SNR = 64.92dBFS SFDR = 64.73dBc
dB
dB
0 5 10 15 20 25 30 35 FREQUENCY - MHz 40 45 50
60 70
80 90 100 110 120 130
60 70
80 90 100 110 120 130
0
5
10
15
20 25 30 35 FREQUENCY - MHz
40
45
50
TPC 2. Single Tone @ 71 MHz
TPC 5. Single Tone @ 121 MHz
0 10 20 30 40 50
0
ENCODE = 105 MSPS AIN = 121MHz (-6dBFS) SNR = 66.9dBFS SFDR = 65.57dBc
10 20 30 40 50
ENCODE = 105 MSPS AIN = 201MHz (-10dBFS) SNR = 66.84dBFS SFDR = 64.57dBc
dB
dB
60 70
80 90 100 110 120 130
60 70
80 90 100 110 120 130
0
5
10
15
20 25 30 35 FREQUENCY - MHz
40
45
50
0
5
10
15
20 25 30 35 FREQUENCY - MHz
40
45
50
TPC 3. Single Tone @ 121 MHz
TPC 6. Single Tone @ 201 MHz
REV. A
-7-
AD10200
0 10 20 30 40 50 0
ENCODE = 105 MSPS AIN = 37MHz & 38MHz (-10dBFS) SFDR = 79.84dBc
10 20 30 40 50
ENCODE = 105 MSPS AIN = 71MHz & 72MHz (-7dBFS) SFDR = 74.8dBc
dBc
70
80 90 100 110 120 130
dBc
0 5 10 15 20 25 30 35 FREQUENCY - MHz 40 45 50
60
60 70
80 90 100 110 120 130
0
5
10
15
20 25 30 35 FREQUENCY - MHz
40
45
50
TPC 7. Two-Tone @ 37 MHz/38 MHz
TPC 10. Two-Tone @ 71 MHz/72 MHz
0 10 20 30 40 50
3.0
ENCODE = 105 MSPS AIN = 120MHz & 121MHz (-7dBFS) SFDR = 63.8dBc
2.5 2.0
1.5
ENCODE = 105 MSPS DNL MAX = 0.486 Codes DNL MIN = 0.431 Codes
LSB
dBc
60 70
80 90 100 110 120 130
1.0 0.5 0.0 0.5 1.0
0
5
10
15
20 25 30 35 FREQUENCY - MHz
40
45
50
0
512
1024
1536
2048
2560
3072
3584
4096
TPC 8. Two-Tone @ 120 MHz/121 MHz
TPC 11. Differential Nonlinearity
3
ENCODE = 105 MSPS INL MAX = 0.874 Codes INL MIN = 0.895 Codes
0 1 2 3 4
ENCODE = 105 MSPS 3dB = 261MHz
2
1
dBFS
LSB
0
5
6
1
7 8 9
2
3
0
512
1024
1536
2048
2560
3072
3584
4096
10 3.0
32.7 62.4 92.1 121.8 151.5 181.2 210.9 240.6 270.3 300.0 MHz
TPC 9. Integral Nonlinearity
TPC 12. Gain Flatness
-8-
REV. A
AD10200
11
10MHz = 1.0149 10 50MHz = 1.085 100MHz = 1.130 150MHz = 1.092 9
8 7 6 5 4
10MHz = 50.22 + j.173 50MHz = 48.79 - j4.2 100MHz = 46.95 - j5.9 150MHz = 48.55 - j4.66
3 2 1 3.0 32.7
62.4
92.1 121.8 151.5 181.2 210.9 240.6 270.3 300.0 MHz
TPC 13. Input Impedance S11
TPC 14. Voltage Standing Wave Ratio (VSWR)
SAMPLE N-1 AIN
SAMPLE N
SAMPLE N+10
SAMPLE N+11
SAMPLE N+1
SAMPLE N+9
ENCODE ENCODE
1/f S
t PD
D11 D0 DATA N 11 DATA N 10 N9 N2 DATA N 1 DATA N
tV
DATA N + 1
Figure 1. Timing Diagram
VCC
VCC
VCC
17k ENCODE 100 8k 100
17k ENCODE
Q1 NPN
8k
VREF OUTPUT
Figure 2. Equivalent Encode Input Circuit
Figure 4. Equivalent Voltage Reference Output Circuit
VCC
VCC
5k 5k AIN
100
50
DIGITAL OUTPUT
7k 7k
Figure 3. Equivalent Digital Output Circuit
Figure 5. Equivalent Analog Input Circuit
REV. A
-9-
AD10200
APPLICATION NOTES
Theory of Operation
The AD10200 is a high-dynamic range dual 12-bit, 105 MHz subrange pipeline converter that uses switched capacitor architecture. The analog input section uses AINA2/AINB2 at 2.048 V p-p with an input impedance of 50 . The analog input includes an ac-coupled wide-band 1:1 transformer, which provides high-dynamic range and SNR while maintaining VSWR and gain flatness. The ADC includes a high-bandwidth linear track/ hold that gives excellent spurious performance up to and beyond the Nyquist rate. The high-bandwidth track/hold has a low jitter of 0.25 ps rms, leading to excellent SNR and SFDR performance. AC-coupled differential PECL/ECL encode inputs are recommended for optimum performance.
USING THE AD10200 ENCODE Input
Often, the cleanest clock source is a crystal oscillator producing a pure sine wave. In this configuration, or with any roughly symmetrical clock input, the input can be ac-coupled and biased to a reference voltage that also provides the ENCODE. This ensures that the reference voltage is centered on the encode signal.
Digital Outputs
The digital outputs are TTL/CMOS-compatible and a separate output power supply pin supports interfacing with 3.3 V logic.
Analog Input
The analog input is a single ended ac-coupled high performance 1:1 transformer with an input impedance of 50 to 105 MHz. The nominal full scale input is 2.048 V p-p. Special care was taken in the design of the analog input section of the AD10200 to prevent damage and corruption of data when the input is overdriven.
Voltage Reference
Any high speed A/D converter is extremely sensitive to the quality of the sampling clock provided by the user. A track/hold circuit is essentially a mixer, and any noise, distortion, or timing jitter on the clock will be combined with the desired signal at the A/D output. For that reason, considerable care has been taken in the design of the ENCODE input of the AD10200, and the user is advised to give commensurate thought to the clock source. The ENCODE input are fully TTL/CMOS compatible. For optimum performance, the AD10200 must be clocked differentially. Note that the ENCODE inputs cannot be driven directly from PECL level signals (VIHD is 3.5 V max). PECL level signals can easily be accommodated by ac coupling as shown in Figure 6. Good performance is obtained using an MC10EL16 in the circuit to drive the encode inputs.
0.1 F PECL GATE 510 510 0.1 F
A stable and accurate 2.5 V voltage reference is designed into the AD10200 (VREFOUT). An external voltage reference is not required.
Timing
The AD10200 provides latched data outputs, with 10 pipeline delays. Data outputs are available one propagation delay (tPD) after the rising edge of the encode command (see Figure 1). The length of the output data lines and loads placed on them should be minimized to reduce transients within the AD10200; these transients can detract from the converter's dynamic performance. The minimum guaranteed conversion rate of the AD10200 is 10 MSPS. At internal clock rates below 10 MSPS, dynamic performance may degrade. Therefore, input clock rates below 10 MHz should be avoided.
GROUNDING AND DECOUPLING Analog and Digital Grounding
AD10200
ENCODE ENCODE
GND
Proper grounding is essential in any high speed, high resolution system. Multilayer printed circuit boards (PCBs) are recommended to provide optimal grounding and power schemes. The use of ground and power planes offers distinct advantages: 1. The minimization of the loop area encompassed by a signal and its return path. 2. The minimization of the impedance associated with ground and power paths. 3. The inherent distributed capacitor formed by the power plane, PCB insulation and ground plane. These characteristics result in both a reduction of electromagnetic interference (EMI) and an overall improvement in performance. It is important to design a layout that prevents noise from coupling to the input signal. Digital signals should not be run in parallel with input signal traces and should be routed away from the input circuitry. The PCB should have a ground plane covering all unused portions of the component side of the board to provide a low impedance path and manage the power and ground currents. The ground plane should be removed from the area near the input pins to reduce stray capacitance.
Figure 6. AC Coupling to ENCODE Inputs
ENCODE Voltage Level Definition
The voltage level definitions for driving ENCODE and ENCODE in differential mode are shown in Figure 7.
ENCODE Inputs
Differential Signal Amplitude (VID) High Differential Input Voltage (VIHD) Low Differential Input Voltage (VILD) Common-Mode Input (VICN)
ENCODE ENCODE VIHD VICM VILD VIHS ENCODE
500 mV min, 750 mV nom 5.0 V max 0 V min 1.25 V min, 1.6 V nom
VID
0.1 F VILS
Figure 7. Differential Input Levels
-10-
REV. A
AD10200
LAYOUT INFORMATION EVALUATION BOARD
The schematic of the evaluation board (Figure 8) represents a typical implementation of the AD10200. The pinout of the AD10200 is very straightforward and facilitates ease of use and the implementation of high frequency/high resolution design practices. It is recommended that high quality ceramic chip capacitors be used to decouple each supply pin to ground directly at the device. All capacitors can be standard high quality ceramic chip capacitors. Care should be taken when placing the digital output runs. Because the digital outputs have such a high-slew rate, the capacitive loading on the digital outputs should be minimized. Circuit traces for the digital outputs should be kept short and connect directly to the receiving gate. Internal circuitry buffers the outputs of the ADC through a resistor network to eliminate the need to externally isolate the device from the receiving gate.
The AD10200 evaluation board (Figure 9) is designed to provide optimal performance for evaluation of the AD10200 analog-to-digital converter. The board encompasses everything needed to ensure the highest level of performance for evaluating the AD10200. The board requires an analog input signal, encode clock and power supply inputs. The clock is buffered on-board to provide clocks for the latches. The digital outputs and out clocks are available at the standard 40-pin connectors J1 and J2. Power to the analog supply pins is connected via banana jacks. The analog supply powers the associated components and the analog section of the AD10200. The digital outputs of the AD10200 are powered via banana jacks with 3.3 V. Contact the factory if additional layout or applications assistance is required.
Figure 8. Evaluation Board Mechanical Layout
REV. A
-11-
U16 25 LE2 DGNDA 3.3VDA C15 10 F B9A B8A B7A DGNDA B6A B5A R71 50 B4A 7 8 9 5 6 4 37 36 35 (MSB) B11A B10A 2 3 39 38 1 40 I15 O15 O14 GND O13 O12 VCC O11 O10 GND O9 O8 O7 O6 GND O5 O4 VCC O3 O2 GND O1 O0 OE1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 BUFLATA 17 18 19 20 21 22 I14 GND I13 I12 VCC I11 I10 GND I9 I8 I7 I6 GND I5 I4 VCC I3 I2 GND I1 I0 LE1 74LCX16374 23 OE2 24 D11A D10A DGNDA D9A D8A DUT_3.3VDA D7A J6 SMA DNS D6A DGNDA D5A D4A D3A D2A 60 AGNDB D1A C36 DNS (LSB) D0A DUT_3.3VDA E50 R51 44 DGNDA R47 46 47 48 R48 0 DGNDA LATCHA 25 D11A D10A DGNDB D9A D8A DUT_3.3VDB D7A 26 27 28 29 30 31 32 D6A DGNDB L3 E6 C3 10 F 47 20% @100MHz U1 C20 0.1 F AGNDA 5AA_ D5A D4A D3A D2A AGNDA DGNDB D1A L4 E5 5AB_ R53 R54 0 AGNDB AGNDB R50 0 DGNDB LATCHB DGNDB R49 0 0 U1 C21 0.1 F C4 10 F 47 20% @100MHz (LSB) D0A DUT_3.3VDB 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 LE2 I15 I14 GND I13 I12 VCC I11 I10 GND I9 I8 I7 I6 GND I5 I4 VCC I3 I2 GND I1 I0 LE1 R8 50 R7 50 U17 OE2 O15 O14 GND O13 O12 VCC O11 O10 GND O9 O8 O7 O6 GND O5 O4 VCC O3 O2 GND O1 O0 OE1 74LCX16374 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 DGNDB R18 100 R17 B10B 100 DGNDB B11B (MSB) 3.3VDB C14 10 F (MSB) B11B B10B B9B B8B B7B DGNDB B6B B5B BUFLATB R72 50 B3B B2B B1B (LSB) B0B B4B 1 2 3 4 5 6 7 8 9 0 45 0.1 F C35 0 AGNDB DUT_3.3VDB D0B D1B D2B D3B DGNDB D4B D5B DGNDB C18 0.1 F U17 0 AGNDB ENCBB ENCB AGNDB R52 43 42 41 AGNDB AGNDB NC 40 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 DGNDA 39 38 37 36 35 34 33 32 31 30 29 E49 AGNDA J7 SMA 28 27 26
AD10200
H40DM J1
J3 SMA DNS 0.1 F C33 AGNDA
J4 SMA
34 33 32
AGNDA
C37 DNS
AGNDA
AGNDA (NC)
AGNDA LID
AGNDB (NC)
5VAB_
AGNDA (NC)
AGNDA
AGNDB
AGNDA
AGNDB
B3A B2A B1A (LSB) B0A F3A F2A F1A F0A DGNDA
10 11 12 13 14 15 16 17 18 19 20
31 30 29 28 27 26 25 24 23 22 21 DGNDA
9 5
7 6
5 4 3 2
1 68
67 66
65 64 63 AGNDB SDIN_B AINB2 AINB1 AGNDB
AGNDB AGNDB VFU_B SDOUT_B REF_B AGNDB ENCBB ENCB AGNDB 3.3VDB D0B (LSB) D1B D2B D3B D4B D5B DGNDB
62
AINA2
AINA1
AGNDA VFU_A
REF_A AGNDA
AGNDA SDIN_A
SHIELD AGNDB
AGNDA
10
AGNDA
AGNDA
NC AGNDA
11 12
5VAA_
13 14
AGNDA SDOUT_A AGNDA
15
C34 0.1 F
5VAA SCLK_A
AGNDA
NC AGNDA ENCAB ENCA
16 17 18
AGNDA ENCAB ENCA
U1
AD10200
AGNDA
AGNDA
DUT_3.3VDA
C10 0.1 F U1
D11A
19 20 21
SCLK_B 5VAB
61
22
3.3VDA D11A (MSBA)
R18 B11A (MSB) 100 R17 B10A 100 DGNDA R16 B9A 100 R40 B8A 100 DUT_3.3VDA R44 B7A 100 R45 B6A 100 DGNDA R46 B5A 100 R15 B4A 100 R14 B3A 100 R13 B2A 100 DGNDA R24 B1A (LSB) 100 R23 B0A 100 DUT_3.3VDA R22 F3A DNS R21 F2A DNS DGNDA R20 F1A DNS R19 F0A DNS DGNDA
DGNDA
D10A D9A D8A
23 24
D10A D9A D8A
DGNDB
27 DGNDA 28 D6A 29 D5A 30 D4A 31 D3A 32 D2A 33 D1A 34 D0A (LSBA)
35 AGNDA 36 AGNDB 37 D11B (MSBB) 38 D10B 39 D9B 40 D8B 41 D7B 42 D6B
NC = NO CONNECT
43
D4A D3A
D2A D1A
D0A
D9B
D8B
DGNDA D6A D5A
AGNDA
AGNDB D11B D10B
DGNDB
Figure 9a. Evaluation Board
D7B D6B
-12-
5AA 5AB
D7A DGNDA
25 26
D7A DGNDA
H40DM J2 40 39 38 37 36 35 34 33 32
3.3VDA
L1
DUT_3.3VDA
E25
C29 10 F
U1 C12 0.1 F
47 20% @100MHz
10 11 12 13 14 15 16 17 18 F3B F2B F1B F0B DGNDB 19 20
31 30 29 28 27 26 25 24 23 22 21 DGNDB
DGNDA
3.3VDB
L2
DUT_3.3VDB
E26
C30 10 F
U8 C16 0.1 F
47 20% @100MHz
DGNDB
R16 B9B 100 R40 B8B 100 DUT_3.3VDB R44 B7B 100 R45 B6B 100 DGNDB R46 B5B 100 R15 B4B 100 R14 B3B 100 R13 B2B 100 DGNDB R24 B1B (LSB) 100 R23 B0B 100 DUT_3.3VDB R22 F3B DNS R21 F2B DNS DGNDB R20 F1B DNS R19 F0B DNS DGNDB
REV. A
AD10200
5 NR 1 3 ERR OUT ADP3330 2 IN SD SD 6 4 1 2 3 4 C2 0.1 F C6 0.1 F 1 2 3 4 U14
+5VAA_
AGNDA
J5 ENCODE SMA AGNDA R1 50
C1 0.1 F J12 SMA R41 50 AGNDA AGNDA DGNDA R58 33k
U2 NC VCC D Q DB QB VBB VEE MC10EL16 R56 33k
C13 0.47 F 8 7 6 5
AGNDA
AGNDA
R42 100 C7 0.1 F ENCAB ENCAB
+3.3VA
R43 100
C8 0.1 F
AGNDA DGNDA
U3 NC VCC D Q DB QB VBB VEE MC10EL16
8 7 6 5
R3 100 1 2 3 4
DGNDA
+3.3VA
U4 D0 VCC D0B Q0 D1B Q1 D1 VEE MC100EPT23
C5 0.1 F 8 7 6 5 +3.3VA
LATCHA E23 E19 BUFLATA
R4 100
DGNDA
1
U15 3 +5VAB_ 2
5 NR 1 ERR OUT ADP3330 IN SD SD 6 4 1 2 3 4
DGNDA
DGNDA
NC = NO CONNECT
AGNDB
J10 ENCODE SMA AGNDB R60 50
C22 0.1 F J11 SMA R61 50 AGNDB AGNDB DGNDB R39 33k
C23 0.1 F C25 0.1 F 1 2 3 4
U11 VCC NC Q D QB DB VEE VBB MC10EL16 R38 33k
C27 0.47 F 8 7 6 5
AGNDB
AGNDB
R63 100 C24 0.1 F ENCBB ENCB
+3.3VB
R64 100
C28 0.1 F
2
AGNDB
U9 VCC NC Q D QB DB VEE VBB MC10EL16
DGNDA
8 7 6 5
R3 100 1 2 3 4
DGNDB
+3.3VDB
R66 100
DGNDB
U10 D0 VCC D0B Q0 D1B Q1 D1 VEE MC100EPT23
C26 0.1 F 8 7 6 5 +3.3VB
LATCHB E24 E22 BUFLATB
DGNDB
DGNDB
NC = NO CONNECT BANANA JACKS FOR GNDS AND PWRS E3 E4 E33 DGNDB AGNDB AGNDA DGNDB E66 E67 E70 E72 E73 E76 E81 DGNDA E29 E36 E38 E40 E45 E79 E84 DGNDB E80 E83 AGNDB E68 E69 E71 E74 E75 E82 AGNDA E30 E35 E37 E39 E46 E42 E44 E48 E41 E43 E47 E65
E34 DGNDA
DGNDB DGNDA
DGNDA
STAND OFFS ON THE BOARD SO1 SO4 SO2 SO5 SO3 SO6
Figure 9b. Evaluation Board
REV. A
-13-
AD10200
BILL OF MATERIALS LIST FOR AD10200 EVAL BOARD Qty. 2 1 2 4 4 8 23 Component Name 74LCX16373MTD AD10200BZ ADP3330 BRES0805 BRES0805 BRES0805 CAP2 Ref Des U16, U17 U1 U14, U15 R38, R39, R56, R58 R1, R41, R60, R61 R3, R4, R42, R43, R63, R64, R65, R66 C1, C2, C5, C6, C7, C8, C9, C10, C12, C16, C17, C18, C20, C21, C22, C23, C24, C25, C26, C28, C33, C34, C35 C13, C27, C38, C39 J1, J2 L1, L2, L3, L4 U2, U3 U9, U11 BJ1 - BJ10 U4, U10 C3, C4, C14, C15, C29, C30 R47, R48, R49, R50, R51, R52, R53, R54 R7, R8, R71, R72 R9, R10, R11, R12, R13, R14, R15, R16, R17, R18, R23, R24, R25, R26, R27, R28, R29, R30, R35, R36, R40, R44, R45, R46 J4 J7 J11, J12 J5, J10 S01-S04 Value Description M/S P/Ns 74LCX16374MTD (Fairchild) AD10200BZ ADP3330ART-3.3-RL7 (Analog) ERJ6GEYJ333V (Panasonic) ERJ6GEYJ510V (Panasonic) ERJ6GEYJ101V (Panasonic) GRM40X7R104K025BL (MENA)
33 k 50 100 0.1 F
SM 3.3 V Regulator SM 0805 Resistor SM 0805 Resistor SM 0805 Resistor SM 0805 Capacitor
4 2 4 4 10 2 6 8
CAP2 N49DM IND2 MC10EL16 BJACK MC100ELT23 POLCAP2 RES2
0.47 F 47
SM 1206 Capacitor 2x20x100 Male Connector Inductor POWER JACK
10 F 0 50
SM 1812 Polar Capacitor SM 0805 Resistor
VJ1206U474MFXMB (VITRAMON) TSW-120-08G-D (Samtec) 2743019447 (Fair Ride) MC1016EP16D (Motorola) 108-0740-001 (Johnson Comp.) SY100ELT23L (Micrel-Synergy) T491C106M016A57280 (KEMET) ERJ-6GEY0R00V (Panasonic)
4 24
RES4 RES2
SM 0805 Resistor
ERJ-6GEYJ510V (Panasonic)
1 1 2 2 4 4 1
SMA SMA SMA SMA Stand-Off Screws PCB
AINA2 AINB2 ENCODE ENCODE Stand-Off Screws (Stand-Off) AD10200 Eval Board
142-0701-201 (Johnson Comp.) 142-0701-201 (Johnson Comp.) 142-0701-201 (Johnson Comp.) 142-0701-201 (Johnson Comp.) 313-2477-016 (Johnson Comp.) MPMS 0040005PH (Building Fasteners) GS03363 Rev. A
-14-
REV. A
C3
C29
R71 R41 R58 C6 U4 C9 R7 R3 R4 U3 R43 R42 C8 C15
R48 R47 R51 R52
GND TIES
C2 R1 C1 U2 C13 U14 R56
C7
C34 C37
E48 U16 GND TIE
C10
C20
GND TIE
GND TIE GND TIE E40
GND TIE
C18
C21 C24
C36
C25 U17 R53 R54 C17 R8 R49 R50 R65 U9
C28 R64
C35 U15 R63 U11 C27 R38 C22 R60
R66 R39
U10
C23 R61
C30
GND TIES
R72
C4 C14
GND TIE
C33
REV. A
Figure 10b. Bottom Assembly
Figure 10a. Bottom View
-15-
AD10200
AD10200
Figure 10c. Ground 1
AGNDB
DGNDB
AGNDA
DGNDA
Figure 10d. Ground 2
-16-
REV. A
C3
C29
R71 R41 R58 C6 U4 C9 R7 R3 R4 U3 R43 R42 C8 C15 E48 C10 C7 C34 C37 C20 GND TIE C33 GND TIE GND TIE GND TIE E40 GND TIE C2 R1 C1 U2 C13 U14 R56
R48
R47
R51
R52
C18
C21 C24
C36
C25 U17 R53 R54 C17 R8 R49 R50 R65 U9
C28 R64
C35 U15 R63 U11 C27 R38 C22 R60
R66 R39
U10
C23 R61
C30
GND TIES
R72
C4 C14
GND TIE
U16
GND TIES
REV. A
Figure 10e. Bottom Silk
Figure 10f. Top View
-17-
AD10200
AD10200
E5 E3 E37 +5VAB AGNDB E30 E29 L2 E38 DGNDB E33 C16 3.3VDB E26 J2
BJ1 EXTRA E27 E63 L4
E2
E1
E35
GND TIES
E36 U6 E79 C39 E59 E58 E62 E55
ENCB
ENCBBAR
E80 J11
J10
E46
E45 C26 E22 E24
E60 E61 BUFLATB LATCHB
E83
E84
AINB1 AINB2 J6 E11 J7 E39 GND TIE E47 J3 J4 AINA1 E49 REF_A
E50 REF_B U1 ANALOG DEVICES COPYRIGHT E12 2/10 00 GND TIE AD10200 EVALUATION BOARD GS03363 (A) E7 BEL
GND TIE
E77
PIN 1
GND TIE E78
E8
AINA2
E19 ENCA ENCABAR E82 J5 J12 E65 E9 E64 E41 E43 BJ2 EXTRA E28 +5VAA AGNDA L3 E68 E74 E71 E69 E75 E6 E4 E81 E66 E10 E42 E44 E67 E73 E72 E70 E76 DGNDA C5 E23
BUFLATA LATCHA E57 E52 E53
E56 E54 U5
E51 C38
GND TIES
C12 E34 E25
Figure 10g. Top Assembly
E5
E3 E37 E38 DGNDB E30 E29
E33 C16
R1 R1 1 R3 0 R2 0 R2 9 R2 8 R2 7 R1 6 R9 2 R2 R3 5 R3 6 R3 5 4 R3 R3 3 R3 2 1
8 R1 7 R1 6 R1 0 R4 4 R4 5 R4 6 R4 5 R1 4 R1 3 R1 4 R2
J1
3 R2 2 R2
L1
1 R2 0 R2
9 R1
3.3VDA
E26
J2 3.3VDB
+5VAB
AGNDB
BJ1 EXTRA E27 E63 L4
E2
GND TIES
E1
L2
E35
E36 U6 E79 C39 E59 E58 E62
R3 R2 0 R2 9 R2 8 R2 7 R1 6 R9 2 R2 R3 5 R3 6 R3 5 R3 4 3 R3 R3 2 1
ENCB
ENCBBAR
E80 J11
J10
E46
E45 C26 E22 E24
E60 E61 BUFLATB LATCHB
E55
E83
E84
AINB1 AINB2 J6 E11
GND TIE
E50 REF_B U1 ANALOG DEVICES COPYRIGHT E12 2/10 00 GND TIE AD10200 EVALUATION BOARD GS03363 (A) E7 BEL
J7 E39 GND TIE E47 J3 J4 AINA1 E49 REF_A
PIN 1
E77 GND TIE E78
E8
R1 R1 1 0
8 R1 7 R1 6 R1 0 R4 4 R4 5 R4 6 R4 5 R1 4 R1 3 R1 4 R2
AINA2
J1
E19 ENCA ENCABAR E82 J5 J12 E65 E9 E64 E41 E43 BJ2 EXTRA E28 +5VAA AGNDA L3 E81 E66 E10 E42 E44 E67 E73 E72 E70 E76 DGNDA C5 E23
BUFLATA LATCHA E57 E52 E53
3 R2 2 R2
E56 E54 U5
E51 C38
1 R2 0 R2 9 R1
E68
GND TIES
E74 E71 E69 E75 E6 E4
L1
3.3VDA C12 E34 E25
Figure 10h. Top Silk
-18-
REV. A
AD10200
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
68-Lead Ceramic Leaded Chip Carrier (Z-68B)
0.290 (7.37) MAX 0.960 (24.38) 0.950 (24.13) SQ 0.940 (23.88)
9 10 PIN 1 61 60
0.010 (0.25) 0.008 (0.20) 0.007 (0.18)
DETAIL A
1.070 (27.18) MIN TOE DOWN ANGLE 0-8 DEGREES
0.800 (20.32) BSC
TOP VIEW
(PINS DOWN)
1.190 (30.23) 1.180 (29.97) SQ 1.170 (29.72)
26 27 43
44
0.060 (1.52) 0.050 (1.27) 0.040 (1.02)
DETAIL A 0.230 (5.84) MAX 0.055 (1.40) 0.050 (1.27) 0.045 (1.14) 0.021 (0.533) 0.017 (0.432) 0.014 (0.357)
Revision History
Location Page
Data Sheet changed from REV. 0 to REV. A. Edit to ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Edit to Figure 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Edit to ENCODE Inputs section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Edit to Figure 9a . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
REV. A
-19-
-20-
C01634-0-8/01(A)
PRINTED IN U.S.A.

▲Up To Search▲

Price & Availability of AD10200

	To Download AD10200 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .